## 12 Flash Commands

OpenOCD has different commands for NOR and NAND flash; the “flash” command works with NOR flash, while the “nand” command works with NAND flash. This partially reflects different hardware technologies: NOR flash usually supports direct CPU instruction and data bus access, while data from a NAND flash must be copied to memory before it can be used. (SPI flash must also be copied to memory before use.) However, the documentation also uses “flash” as a generic term; for example, “Put flash configuration in board-specific files”.

Flash Steps:

1. Configure via the command `flash bank`
   Do this in a board-specific configuration file, passing parameters as needed by the driver.
2. Operate on the flash via `flash subcommand`
   Often commands to manipulate the flash are typed by a human, or run via a script in some automated way. Common tasks include writing a boot loader, operating system, or other data.
3. GDB Flashing
   Flashing via GDB requires the flash be configured via “flash bank”, and the GDB flash features be enabled. See GDB Configuration.

Many CPUs have the ablity to “boot” from the first flash bank. This means that misprogramming that bank can “brick” a system, so that it can't boot. JTAG tools, like OpenOCD, are often then used to “de-brick” the board by (re)installing working boot firmware.

### 12.1 Flash Configuration Commands

— Config Command: flash bank name driver base size chip_width bus_width target [driver_options]

> Configures a flash bank which provides persistent storage for addresses from base to base + size - 1. These banks will often be visible to GDB through the target's memory map. In some cases, configuring a flash bank will activate extra commands; see the driver-specific documentation.

> - name ... may be used to reference the flash bank in other flash commands. A number is also available.
> - driver ... identifies the controller driver associated with the flash bank being declared. This is usually `cfi` for external flash, or else the name of a microcontroller with embedded flash memory. See Flash Driver List.
> - base ... Base address of the flash chip.
> - size ... Size of the chip, in bytes. For some drivers, this value is detected from the hardware.
> - chip_width ... Width of the flash chip, in bytes; ignored for most microcontroller drivers.
> - bus_width ... Width of the data bus used to access the chip, in bytes; ignored for most microcontroller drivers.
> - target ... Names the target used to issue commands to the flash controller.
> - driver_options ... drivers may support, or require, additional parameters. See the driver-specific documentation for more information.

> > Note: This command is not available after OpenOCD initialization has completed. Use it in board specific configuration files, not interactively.

— Command: flash banks

> Prints a one-line summary of each device that was declared using `flash bank`, numbered from zero. Note that this is the plural form; the singular form is a very different command.

— Command: flash list

> Retrieves a list of associative arrays for each device that was declared using `flash bank`, numbered from zero. This returned list can be manipulated easily from within scripts.

— Command: flash probe num

> Identify the flash, or validate the parameters of the configured flash. Operation depends on the flash type. The num parameter is a value shown by `flash banks`. Most flash commands will implicitly autoprobe the bank; flash drivers can distinguish between probing and autoprobing, but most don't bother.

### 12.2 Erasing, Reading, Writing to Flash

One feature distinguishing NOR flash from NAND or serial flash technologies is that for read access, it acts exactly like any other addressible memory. This means you can use normal memory read commands like `mdw` or `dump_image` with it, with no special `flash` subcommands. See Memory access, and Image access.

Write access works differently. Flash memory normally needs to be erased before it's written. Erasing a sector turns all of its bits to ones, and writing can turn ones into zeroes. This is why there are special commands for interactive erasing and writing, and why GDB needs to know which parts of the address space hold NOR flash memory.

> Note: Most of these erase and write commands leverage the fact that NOR flash chips consume target address space. They implicitly refer to the current JTAG target, and map from an address in that target's address space back to a flash bank. A few commands use abstract addressing based on bank and sector numbers, and don't depend on searching the current target and its address space. Avoid confusing the two command models.

Some flash chips implement software protection against accidental writes, since such buggy writes could in some cases “brick” a system. For such systems, erasing and writing may require sector protection to be disabled first. Examples include CFI flash such as “Intel Advanced Bootblock flash”, and AT91SAM7 on-chip flash. See flash protect.

— Command: flash erase_sector num first last

> Erase sectors in bank num, starting at sector first up to and including last. Sector numbering starts at 0. Providing a last sector of `last` specifies "to the end of the flash bank". The num parameter is a value shown by `flash banks`.

— Command: flash erase_address [`pad`] [`unlock`] address length

> Erase sectors starting at address for length bytes. Unless `pad` is specified, address must begin a flash sector, and address + length - 1 must end a sector. Specifying `pad` erases extra data at the beginning and/or end of the specified region, as needed to erase only full sectors. The flash bank to use is inferred from the address, and the specified length must stay within that bank. As a special case, when length is zero and address is the start of the bank, the whole flash is erased. If `unlock` is specified, then the flash is unprotected before erase starts.

— Command: flash fillw address word length
— Command: flash fillh address halfword length
— Command: flash fillb address byte length

> Fills flash memory with the specified word (32 bits), halfword (16 bits), or byte (8-bit) pattern, starting at address and continuing for length units (word/halfword/byte). No erasure is done before writing; when needed, that must be done before issuing this command. Writes are done in blocks of up to 1024 bytes, and each write is verified by reading back the data and comparing it to what was written. The flash bank to use is inferred from the address of each block, and the specified length must stay within that bank.

— Command: flash write_bank num filename offset

> Write the binary `filename` to flash bank num, starting at offset bytes from the beginning of the bank. The num parameter is a value shown by `flash banks`.

— Command: flash write_image [erase] [unlock] filename [offset] [type]

> Write the image `filename` to the current target's flash bank(s). A relocation offset may be specified, in which case it is added to the base address for each section in the image. The file [type] can be specified explicitly as `bin` (binary), `ihex` (Intel hex), `elf` (ELF file), `s19` (Motorola s19). `mem`, or `builder`. The relevant flash sectors will be erased prior to programming if the `erase` parameter is given. If `unlock` is provided, then the flash banks are unlocked before erase and program. The flash bank to use is inferred from the address of each image section.

> > Warning: Be careful using the `erase` flag when the flash is holding data you want to preserve. Portions of the flash outside those described in the image's sections might be erased with no notice.
> > - When a section of the image being written does not fill out all the sectors it uses, the unwritten parts of those sectors are necessarily also erased, because sectors can't be partially erased.
> > - Data stored in sector "holes" between image sections are also affected. For example, "`flash write_image erase ...`" of an image with one byte at the beginning of a flash bank and one byte at the end erases the entire bank – not just the two sectors being written.
> > Also, when flash protection is important, you must re-apply it after it has been removed by the `unlock` flag.

### 12.3 Other Flash commands

— Command: flash erase_check num

> Check erase state of sectors in flash bank num, and display that status. The num parameter is a value shown by `flash banks`.

— Command: flash info num

> Print info about flash bank num The num parameter is a value shown by `flash banks`. This command will first query the hardware, it does not print cached and possibly stale information.

— Command: flash protect num first last (`on`|`off`)

> Enable (`on`) or disable (`off`) protection of flash sectors in flash bank num, starting at sector first and continuing up to and including last. Providing a last sector of `last` specifies "to the end of the flash bank". The num parameter is a value shown by `flash banks`.

### 12.4 Flash Driver List

As noted above, the `flash bank` command requires a driver name, and allows driver-specific options and behaviors. Some drivers also activate driver-specific commands.

#### 12.4.1 External Flash

— Flash Driver: cfi

> The “Common Flash Interface” (CFI) is the main standard for external NOR flash chips, each of which connects to a specific external chip select on the CPU. Frequently the first such chip is used to boot the system. Your board's `reset-init` handler might need to configure additional chip selects using other commands (like: `mww` to configure a bus and its timings), or perhaps configure a GPIO pin that controls the “write protect” pin on the flash chip. The CFI driver can use a target-specific working area to significantly speed up operation.

> The CFI driver can accept the following optional parameters, in any order:

> - jedec_probe ... is used to detect certain non-CFI flash ROMs, like AM29LV010 and similar types.
> - x16_as_x8 ... when a 16-bit flash is hooked up to an 8-bit bus.

> To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes) wide on a sixteen bit bus:

>               flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
>               flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME

> To configure one bank of 32 MBytes built from two sixteen bit (two byte) wide parts wired in parallel to create a thirty-two bit (four byte) bus with doubled throughput:

>               flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME

— Flash Driver: stmsmi

> Some devices form STMicroelectronics (e.g. STR75x MCU family, SPEAr MPU family) include a proprietary “Serial Memory Interface” (SMI) controller able to drive external SPI flash devices. Depending on specific device and board configuration, up to 4 external flash devices can be connected.

> SMI makes the flash content directly accessible in the CPU address space; each external device is mapped in a memory bank. CPU can directly read data, execute code and boot from SMI banks. Normal OpenOCD commands like `mdw` can be used to display the flash content.

> The setup command only requires the base parameter in order to identify the memory bank. All other parameters are ignored. Additional information, like flash size, are detected automatically.

>               flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME

#### 12.4.2 Internal Flash (Microcontrollers)

— Flash Driver: aduc702x

> The ADUC702x analog microcontrollers from Analog Devices include internal flash and use ARM7TDMI cores. The aduc702x flash driver works with models ADUC7019 through ADUC7028. The setup command only requires the target argument since all devices in this family have the same memory layout.

>               flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME

— Flash Driver: at91sam3

> All members of the AT91SAM3 microcontroller family from Atmel include internal flash and use ARM's Cortex-M3 core. The driver currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note that the driver was orginaly developed and tested using the AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in the family was cribbed from the data sheet. Note to future readers/updaters: Please remove this worrysome comment after other chips are confirmed.

> The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips have one flash bank. In all cases the flash banks are at the following fixed locations:

>               # Flash bank 0 - all chips
>               flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
>               # Flash bank 1 - only 256K chips
>               flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME

> Internally, the AT91SAM3 flash memory is organized as follows. Unlike the AT91SAM7 chips, these are not used as parameters to the `flash bank` command:

> - N-Banks: 256K chips have 2 banks, others have 1 bank.
> - Bank Size: 128K/64K Per flash bank
> - Sectors: 16 or 8 per bank
> - SectorSize: 8K Per Sector
> - PageSize: 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.

> The AT91SAM3 driver adds some additional commands:

> — Command: at91sam3 gpnvm
> — Command: at91sam3 gpnvm clear number
> — Command: at91sam3 gpnvm set number
> — Command: at91sam3 gpnvm show [`all`|number]

> > With no parameters, `show` or `show all`, shows the status of all GPNVM bits. With `show` number, displays that bit.

> > With `set` number or `clear` number, modifies that GPNVM bit.

> — Command: at91sam3 info

> > This command attempts to display information about the AT91SAM3 chip. First it read the `CHIPID_CIDR` [address 0x400e0740, see Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet, document id: doc6430A] and decodes the values. Second it reads the various clock configuration registers and attempts to display how it believes the chip is configured. By default, the SLOWCLK is assumed to be 32768 Hz, see the command `at91sam3 slowclk`.

> — Command: at91sam3 slowclk [value]

> > This command shows/sets the slow clock frequency used in the `at91sam3 info` command calculations above.

— Flash Driver: at91sam7

> All members of the AT91SAM7 microcontroller family from Atmel include internal flash and use ARM7TDMI cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.

>               flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME

> For chips which are not recognized by the controller driver, you must provide additional parameters in the following order:

> - chip_model ... label used with `flash info`
> - banks
> - sectors_per_bank
> - pages_per_sector
> - pages_size
> - num_nvm_bits
> - freq_khz ... required if an external clock is provided, optional (but recommended) when the oscillator frequency is known

> It is recommended that you provide zeroes for all of those values except the clock frequency, so that everything except that frequency will be autoconfigured. Knowing the frequency helps ensure correct timings for flash access.

> The flash controller handles erases automatically on a page (128/256 byte) basis, so explicit erase commands are not necessary for flash programming. However, there is an “EraseAll“ command that can erase an entire flash plane (of up to 256KB), and it will be used automatically when you issue `flash erase_sector` or `flash erase_address` commands.

> — Command: at91sam7 gpnvm bitnum (`set`|`clear`)

> > Set or clear a “General Purpose Non-Volatile Memory” (GPNVM) bit for the processor. Each processor has a number of such bits, used for controlling features such as brownout detection (so they are not truly general purpose).

> > > Note: This assumes that the first flash bank (number 0) is associated with the appropriate at91sam7 target.

— Flash Driver: avr

> The AVR 8-bit microcontrollers from Atmel integrate flash memory. The current implementation is incomplete.

— Flash Driver: ecosflash

> No idea what this is... The ecosflash driver defines one mandatory parameter, the name of a modules of target code which is downloaded and executed.

— Flash Driver: lpc2000

> Most members of the LPC1700 and LPC2000 microcontroller families from NXP include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.

> > Note: There are LPC2000 devices which are not supported by the lpc2000 driver: The LPC2888 is supported by the lpc288x driver. The LPC29xx family is supported by the lpc2900 driver.

> The lpc2000 driver defines two mandatory and one optional parameters, which must appear in the following order:

> - variant ... required, may be `lpc2000_v1` (older LPC21xx and LPC22xx) `lpc2000_v2` (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx) or `lpc1700` (LPC175x and LPC176x)
> - clock_kHz ... the frequency, in kiloHertz, at which the core is running
> - `calc_checksum` ... optional (but you probably want to provide this!), telling the driver to calculate a valid checksum for the exception vector table.

>   > Note: If you don't provide `calc_checksum` when you're writing the vector table, the boot ROM will almost certainly ignore your flash image. However, if you do provide it, with most tool chains `verify_image` will fail.

> LPC flashes don't require the chip and bus width to be specified.

>               flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
>                     lpc2000_v2 14765 calc_checksum

> — Command: lpc2000 part_id bank

> > Displays the four byte part identifier associated with the specified flash bank.

— Flash Driver: lpc288x

> The LPC2888 microcontroller from NXP needs slightly different flash support from its lpc2000 siblings. The lpc288x driver defines one mandatory parameter, the programming clock rate in Hz. LPC flashes don't require the chip and bus width to be specified.

>               flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000

— Flash Driver: lpc2900

> This driver supports the LPC29xx ARM968E based microcontroller family from NXP.

> The predefined parameters base, size, chip_width and bus_width of the `flash bank` command are ignored. Flash size and sector layout are auto-configured by the driver. The driver has one additional mandatory parameter: The CPU clock rate (in kHz) at the time the flash operations will take place. Most of the time this will not be the crystal frequency, but a higher PLL frequency. The `reset-init` event handler in the board script is usually the place where you start the PLL.

> The driver rejects flashless devices (currently the LPC2930).

> The EEPROM in LPC2900 devices is not mapped directly into the address space. It must be handled much more like NAND flash memory, and will therefore be handled by a separate `lpc2900_eeprom` driver (not yet available).

> Sector protection in terms of the LPC2900 is handled transparently. Every time a sector needs to be erased or programmed, it is automatically unprotected. What is shown as protection status in the `flash info` command, is actually the LPC2900 sector security. This is a mechanism to prevent a sector from ever being erased or programmed again. As this is an irreversible mechanism, it is handled by a special command (`lpc2900 secure_sector`), and not by the standard `flash protect` command.

> Example for a 125 MHz clock frequency:

>               flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000

> Some `lpc2900`-specific commands are defined. In the following command list, the bank parameter is the bank number as obtained by the `flash banks` command.

> — Command: lpc2900 signature bank

> > Calculates a 128-bit hash value, the signature, from the whole flash content. This is a hardware feature of the flash block, hence the calculation is very fast. You may use this to verify the content of a programmed device against a known signature. Example:

> >                    lpc2900 signature 0
> >                      signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317

> — Command: lpc2900 read_custom bank filename

> > Reads the 912 bytes of customer information from the flash index sector, and saves it to a file in binary format. Example:

> >                    lpc2900 read_custom 0 /path_to/customer_info.bin

> The index sector of the flash is a write-only sector. It cannot be erased! In order to guard against unintentional write access, all following commands need to be preceeded by a successful call to the `password` command:

> — Command: lpc2900 password bank password

> > You need to use this command right before each of the following commands: `lpc2900 write_custom`, `lpc2900 secure_sector`, `lpc2900 secure_jtag`.

> > The password string is fixed to "I_know_what_I_am_doing". Example:

> >                    lpc2900 password 0 I_know_what_I_am_doing
> >                      Potentially dangerous operation allowed in next command!

> — Command: lpc2900 write_custom bank filename type

> > Writes the content of the file into the customer info space of the flash index sector. The filetype can be specified with the type field. Possible values for type are: bin (binary), ihex (Intel hex format), elf (ELF binary) or s19 (Motorola S-records). The file must contain a single section, and the contained data length must be exactly 912 bytes.

> > > Attention: This cannot be reverted! Be careful!

> > Example:

> >                    lpc2900 write_custom 0 /path_to/customer_info.bin bin

> — Command: lpc2900 secure_sector bank first last

> > Secures the sector range from first to last (including) against further program and erase operations. The sector security will be effective after the next power cycle.

> > > Attention: This cannot be reverted! Be careful!

> > Secured sectors appear as protected in the `flash info` command. Example:

> >                    lpc2900 secure_sector 0 1 1
> >                    flash info 0
> >                      #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
> >                              #  0: 0x00000000 (0x2000 8kB) not protected
> >                              #  1: 0x00002000 (0x2000 8kB) protected
> >                              #  2: 0x00004000 (0x2000 8kB) not protected

> — Command: lpc2900 secure_jtag bank

> > Irreversibly disable the JTAG port. The new JTAG security setting will be effective after the next power cycle.

> > > Attention: This cannot be reverted! Be careful!

> > Examples:

> >                    lpc2900 secure_jtag 0

— Flash Driver: ocl

> No idea what this is, other than using some arm7/arm9 core.

>               flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME

— Flash Driver: pic32mx

> The PIC32MX microcontrollers are based on the MIPS 4K cores, and integrate flash memory.

>               flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
>               flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME

> Some pic32mx-specific commands are defined:

> — Command: pic32mx pgm_word address value bank

> > Programs the specified 32-bit value at the given address in the specified chip bank.

> — Command: pic32mx unlock bank

> > Unlock and erase specified chip bank. This will remove any Code Protection.

— Flash Driver: stellaris

> All members of the Stellaris LM3Sxxx microcontroller family from Texas Instruments include internal flash and use ARM Cortex M3 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. 1

>               flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME

— Command: stellaris recover bank_id

> Performs the Recovering a "Locked" Device procedure to restore the flash specified by bank_id and its associated nonvolatile registers to their factory default values (erased). This is the only way to remove flash protection or re-enable debugging if that capability has been disabled.

> Note that the final "power cycle the chip" step in this procedure must be performed by hand, since OpenOCD can't do it.

> > Warning: if more than one Stellaris chip is connected, the procedure is applied to all of them.

— Flash Driver: stm32f1x

> All members of the STM32f1x microcontroller family from ST Microelectronics include internal flash and use ARM Cortex M3 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.

>               flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME

> Some stm32f1x-specific commands 2 are defined:

> — Command: stm32f1x lock num

> > Locks the entire stm32 device. The num parameter is a value shown by `flash banks`.

> — Command: stm32f1x unlock num

> > Unlocks the entire stm32 device. The num parameter is a value shown by `flash banks`.

> — Command: stm32f1x options_read num

> > Read and display the stm32 option bytes written by the `stm32f1x options_write` command. The num parameter is a value shown by `flash banks`.

> — Command: stm32f1x options_write num (`SWWDG`|`HWWDG`) (`RSTSTNDBY`|`NORSTSTNDBY`) (`RSTSTOP`|`NORSTSTOP`)

> > Writes the stm32 option byte with the specified values. The num parameter is a value shown by `flash banks`.

— Flash Driver: stm32f2x

> All members of the STM32f2x microcontroller family from ST Microelectronics include internal flash and use ARM Cortex M3 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.

— Flash Driver: str7x

> All members of the STR7 microcontroller family from ST Microelectronics include internal flash and use ARM7TDMI cores. The str7x driver defines one mandatory parameter, variant, which is either `STR71x`, `STR73x` or `STR75x`.

>               flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x

> — Command: str7x disable_jtag bank

> > Activate the Debug/Readout protection mechanism for the specified flash bank.

— Flash Driver: str9x

> Most members of the STR9 microcontroller family from ST Microelectronics include internal flash and use ARM966E cores. The str9 needs the flash controller to be configured using the `str9x flash_config` command prior to Flash programming.

>               flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
>               str9x flash_config 0 4 2 0 0x80000

> — Command: str9x flash_config num bbsr nbbsr bbadr nbbadr

> > Configures the str9 flash controller. The num parameter is a value shown by `flash banks`.

> > - bbsr - Boot Bank Size register
> > - nbbsr - Non Boot Bank Size register
> > - bbadr - Boot Bank Start Address register
> > - nbbadr - Boot Bank Start Address register

— Flash Driver: tms470

> Most members of the TMS470 microcontroller family from Texas Instruments include internal flash and use ARM7TDMI cores. This driver doesn't require the chip and bus width to be specified.

> Some tms470-specific commands are defined:

> — Command: tms470 flash_keyset key0 key1 key2 key3

> > Saves programming keys in a register, to enable flash erase and write commands.

> — Command: tms470 osc_mhz clock_mhz

> > Reports the clock speed, which is used to calculate timings.

> — Command: tms470 plldis (0|1)

> > Disables (1) or enables (0) use of the PLL to speed up the flash clock.

— Flash Driver: virtual

> This is a special driver that maps a previously defined bank to another address. All bank settings will be copied from the master physical bank.

> The virtual driver defines one mandatory parameters,

> - master_bank The bank that this virtual address refers to.

> So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to the flash bank defined at address 0x1fc00000. Any cmds executed on the virtual banks are actually performed on the physical banks.

>               flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
>               flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
>               flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME

— Flash Driver: fm3

> All members of the FM3 microcontroller family from Fujitsu include internal flash and use ARM Cortex M3 cores. The fm3 driver uses the target parameter to select the correct bank config, it can currently be one of the following: `mb9bfxx1.cpu`, `mb9bfxx2.cpu`, `mb9bfxx3.cpu`, `mb9bfxx4.cpu`, `mb9bfxx5.cpu` or `mb9bfxx6.cpu`.

>               flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME

#### 12.4.3 str9xpec driver

Here is some background info to help you better understand how this driver works. OpenOCD has two flash drivers for the str9:

1. Standard driver `str9x` programmed via the str9 core. Normally used for flash programming as it is faster than the `str9xpec` driver.
2. Direct programming `str9xpec` using the flash controller. This is an ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9 core does not need to be running to program using this flash driver. Typical use for this driver is locking/unlocking the target and programming the option bytes.

Before we run any commands using the `str9xpec` driver we must first disable the str9 core. This example assumes the `str9xpec` driver has been configured for flash bank 0.

         # assert srst, we do not want core running
         # while accessing str9xpec flash driver
         jtag_reset 0 1
         # turn off target polling
         poll off
         # disable str9 core
         str9xpec enable_turbo 0
         # read option bytes
         str9xpec options_read 0
         # re-enable str9 core
         str9xpec disable_turbo 0
         poll on
         reset halt

The above example will read the str9 option bytes. When performing a unlock remember that you will not be able to halt the str9 - it has been locked. Halting the core is not required for the `str9xpec` driver as mentioned above, just issue the commands above manually or from a telnet prompt.

— Flash Driver: str9xpec

> Only use this driver for locking/unlocking the device or configuring the option bytes. Use the standard str9 driver for programming. Before using the flash commands the turbo mode must be enabled using the `str9xpec enable_turbo` command.

> Several str9xpec-specific commands are defined:

> — Command: str9xpec disable_turbo num

> > Restore the str9 into JTAG chain.

> — Command: str9xpec enable_turbo num

> > Enable turbo mode, will simply remove the str9 from the chain and talk directly to the embedded flash controller.

> — Command: str9xpec lock num

> > Lock str9 device. The str9 will only respond to an unlock command that will erase the device.

> — Command: str9xpec part_id num

> > Prints the part identifier for bank num.

> — Command: str9xpec options_cmap num (`bank0`|`bank1`)

> > Configure str9 boot bank.

> — Command: str9xpec options_lvdsel num (`vdd`|`vdd_vddq`)

> > Configure str9 lvd source.

> — Command: str9xpec options_lvdthd num (`2.4v`|`2.7v`)

> > Configure str9 lvd threshold.

> — Command: str9xpec options_lvdwarn bank (`vdd`|`vdd_vddq`)

> > Configure str9 lvd reset warning source.

> — Command: str9xpec options_read num

> > Read str9 option bytes.

> — Command: str9xpec options_write num

> > Write str9 option bytes.

> — Command: str9xpec unlock num

> > unlock str9 device.

### 12.5 mFlash

#### 12.5.1 mFlash Configuration

— Config Command: mflash bank soc base RST_pin target

> Configures a mflash for soc host bank at address base. The pin number format depends on the host GPIO naming convention. Currently, the mflash driver supports s3c2440 and pxa270.

> Example for s3c2440 mflash where RST pin is GPIO B1:

>               mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0

> Example for pxa270 mflash where RST pin is GPIO 43:

>               mflash bank $_FLASHNAME pxa270 0x08000000 43 0

#### 12.5.2 mFlash commands

— Command: mflash config pll frequency

> Configure mflash PLL. The frequency is the mflash input frequency, in Hz. Issuing this command will erase mflash's whole internal nand and write new pll. After this command, mflash needs power-on-reset for normal operation. If pll was newly configured, storage and boot(optional) info also need to be update.

— Command: mflash config boot

> Configure bootable option. If bootable option is set, mflash offer the first 8 sectors (4kB) for boot.

— Command: mflash config storage

> Configure storage information. For the normal storage operation, this information must be written.

— Command: mflash dump num filename offset size

> Dump size bytes, starting at offset bytes from the beginning of the bank num, to the file named filename.

— Command: mflash probe

> Probe mflash.

— Command: mflash write num filename offset

> Write the binary file filename to mflash bank num, starting at offset bytes from the beginning of the bank.

#### Footnotes

[1] Currently there is a `stellaris mass_erase` command. That seems pointless since the same effect can be had using the standard `flash erase_address` command.

[2] Currently there is a `stm32f1x mass_erase` command. That seems pointless since the same effect can be had using the standard `flash erase_address` command.